1. Technical Field
The present disclosure relates to a duty cycle correction apparatus, and in particular, to the duty cycle correction apparatus capable of fast adjusting the internal clocks to have the specific duty cycles.
2. Description of Related Art
The duty cycle correction apparatus is used to correct or adjust duty cycles of complementary internal clocks in the electronic apparatus, such that the duty cycles are not less or larger than the required duty cycle, and the external noise disturbance is avoided. The conventional duty cycle correction apparatus can use the analog signals and digital signals to adjust the duty cycles of the internal clocks in the electronic apparatus. The manner which the analog signals are used to adjust the duty cycles of the internal clocks has the fast adjusting speed, but cannot be applied in the power saving mode (the analog signals will be disappeared). In addition, the manner which the digital signals are used to adjust the duty cycles of the internal clocks can be applied in the power saving mode (the digital signals can be recorded), but has the slow adjusting speed.
Referring to FIG. 1, FIG. 1 is a schematic diagram of a conventional duty cycle correction apparatus. The conventional duty cycle correction apparatus comprises a duty cycle corrector 11, a pump circuit 12, capacitors C1, C2, a comparator 13, a switch SW1, a counter 15 and a digital-analog converter (DAC) 14, wherein the duty cycle corrector 11 is electrically connected to the pump circuit 12, the pump circuit 12 is electrically connected to the comparator 13 and the duty cycle corrector 11, two ends of the capacitor C1 are respectively electrically connected to the pump circuit 12 and a grounding end, two ends of the capacitor C2 are respectively electrically connected to the pump circuit 12 and the grounding end, the comparator 13 is electrically connected to the counter 15 via the switch SW1, the counter 15 is electrically connected to the digital-analog converter 14 and the digital-analog converter 14 is electrically connected to the duty cycle corrector 11.
The duty cycle corrector 11 receives complementary external clocks xclk and xclkn, and generates complementary internal clocks clk and clkn according to the external clocks xclk and xclkn. Next, the pump circuit 12 receives the internal clocks clk and clkn, and generates the complementary feedback clocks fck and fckb according to the internal clocks clk and clkn, wherein since two output ends of the pump circuit 12 are electrically connected to the grounding end respectively via the two capacitors C1 and C2, the feedback clocks fck and fckb are analog integration signals of the internal clocks clk and clkn. The feedback clocks fck and fckb are feedbacked to the duty cycle corrector 11 to fast adjust the internal clocks clk and clkn. It is noted that, in the power saving mode, the feedback clocks fck and fckb leakage via the capacitors C1 and C2 respectively, such that the feedback clocks fck and fckb will be disappeared.
After the feedback clocks fck and fckb are used to fast adjust the internal clocks clk and clkn, the switch SW1 is turned on. Next, the comparator 13 compares the feedback clocks fck and fckb, and generates a comparison signal to the counter 15. The counter 15 generates complementary digital signals Dcreg and Dcregb according to the comparison signal. The digital-analog converter 14 generates complementary signals creg and cregb according to the complementary digital signals Dcreg and Dcregb, and feedbacks the signals creg and cregb to the duty cycle corrector 11 to adjust the internal clocks clk and clkn. It is noted that, after the duty cycles of the internal clocks clk and clkn are adjusted to equal to the required duty cycles, codes of the signals creg and cregb are recorded to be utilized in the next adjustment. Each time the comparator 13 performs comparison, the comparator 13 starts to perform comparison while the amplitude deviation between the feedback clocks fck and fckb reaches a specific value, and thus the adjusting speed is slow.
Referring to FIG. 1 and FIG. 2, FIG. 2 is a schematic diagram which the conventional duty cycle correction apparatus adjusts the duty cycles of the internal clocks to equal to the required duty cycles. Firstly, before time T1, the conventional duty cycle correction apparatus 1 uses the feedback clocks fck and fckb to fast adjust the duty cycles of the internal clocks clk and clkn, and next, the switch SW1 is turned on to be conductive, such that the signal creg (or cregb) with the digital code being 32 and its complementary signal cregb (or creg) are obtained. After time T1, the sequentially feedbacked signals creg and cregb are used to gradually replace the analog signals (i.e. feedback clocks fck and fckb) to adjust the duty cycles of the internal clocks clk and clkn to equal to the required duty cycles. As shown in FIG. 2, the signal creg (or cregb) with the code being 33 and its complementary signal cregb (or creg) are firstly used to adjust the duty cycle of the internal clocks clk and clkn. The example in FIG. 2 is a worst case, the duty cycles of the internal clocks clk and clkn are adjusted to equal to the required duty cycles until the signal creg (or cregb) with the digital code being 63 and its complementary signal cregb (or creg) are used to adjust the duty cycles of the internal clocks clk and clkn.
Assuming double data rate 1 synchronous dynamic random access memory (DDR1 SDRAM) is used to access the signals creg and cregb, each consuming time that the signals creg and cregb are used to adjust the internal clocks clk and clkn is about 32 system clocks (tcks), and thus in the condition of FIG. 2, it cost 31*32=992 system clocks (992 tcks) to obtain the digital codes which make the duty cycle of the internal clocks clk and clkn equal to the required duty cycles.
Referring to FIG. 1 and FIG. 3, FIG. 3 is one other schematic diagram which the conventional duty cycle correction apparatus adjusts the duty cycles of the internal clocks to equal to the required duty cycles. Being different from FIG. 2, in the example of FIG. 3, the switch SW1 is firstly turned on to be conductive, and the signal creg (or cregb) with the digital code being 32 and it complementary signal cregb (or creg) are used to adjust the duty cycles of the internal clocks clk and clkn. Then, by the help of the binary search, the signals creg (or cregb) with the digital codes being 48, 56, 60, and 62 and their complementary signals cregb (or creg) are used to sequentially adjust the duty cycles of the internal clocks clk and clkn. The example of FIG. 3 is a worst case, the duty cycles of the internal clocks clk and clkn are adjusted to equal to the required duty cycles until the signal creg (or cregb) with the digital code being 63 and its complementary signal cregb (or creg) are used to adjust the duty cycles of the internal clocks clk and clkn. Next, after time T2, the feedback clocks fck and fckb are activated to fast adjust the duty cycles of the internal clocks clk and clkn.
Assuming double data rate 1 synchronous dynamic random access memory (DDR1 SDRAM) is used to access the signals creg and cregb, each consuming time that the signals creg and cregb are used to adjust the internal clocks clk and clkn is about 32 system clocks (tcks), and thus in the condition of FIG. 3, it cost 5*32=160 system clocks (160 tcks) to obtain the digital codes which make the duty cycles of the internal clocks clk and clkn equal to the required duty cycles.
As the above descriptions, the consuming time which the conventional duty cycle correction apparatus finds the digital codes corresponding to the required duty cycle is long, and the consuming time may be reduced by other manners.